The present invention relates to a method for controlling a data transfer unit and also to a data transfer unit, a channel control unit, and a storage device control unit.
DMA (Direct Memory Access) transfer technology using a DMA controller has been widely used as a method for transferring data directly between a memory and a device, and not via a CPU. In the DMA transfer, the CPU instructs to conduct data transfer processing by setting the information necessary for data transfer, such as data transfer source and destination, into the DMA controller. If the instruction to conduct data transfer processing is provided, the DMA controller conducts transfer processing of data, without the CPU.
However, with the conventional DMA transfer processing, because the CPU sets the information, such as data transfer source, directly into the DMA controller register, the time required for setting the data by the CPU into the DMA controller cannot be ignored, especially when data transfer processing is conducted frequently. Furthermore, if the DMA controller completes the data transfer processing, it notifies the CPU to this effect, for example, by interruption. However, as the number of data transfer processing operations increases, the number of notifications sent from the DMA controller to CPU also increases and the CPU processing is interrupted for each notification.